A configuration has been known that performs reception processing by means of direct discrete time sampling of a high-frequency signal with the aim of achieving small size and low power consumption of a receiver and integrating the analog signal processing section and digital signal processing section (see, for example, Patent Literature 1 and Non-Patent Literature 1).
FIG. 1 shows the overall configuration of a sampling circuit disclosed in Patent Literature 1. FIG. 2 is a timing chart showing control signals inputted to the circuit shown in FIG. 1. The sampling circuit shown in FIG. 1 performs frequency conversion on a received analog RF signal using a multi-tap direct sampling mixer to obtain a discrete time analog signal. To be more specific, electrical charge transfer between a plurality of capacitors included in the sampling circuit in FIG. 1 realizes filter characteristics resulting in the product of an FIR (finite impulse response) filer and an IIR (infinite impulse response) filter. Characteristics around the passband are determined based on second-order IIR filter characteristics. FIG. 3B shows an example of wideband frequency characteristics (local (LO) frequency fLO=800 MHz). Here, FIG. 3A shows the narrowband frequency characteristic around the passband (800 MHz), in the frequency characteristic shown in FIG. 3B.
Moreover, a configuration in which image rejection can be performed, has been known as a technology based on the above-described configuration (see Patent Literature 2). FIG. 4 shows the whole configuration of a sampling circuit disclosed in Patent Literature 2. FIG. 5 shows an example of frequency characteristics obtained in the circuit shown in FIG. 4 (local (LO) frequency fLO=800 MHz). As shown in FIG. 4, the frequency characteristics are bilaterally asymmetric with respect to the LO frequency and allow image rejection.
Moreover, as a discrete time direct sampling mixer that can realize high-order IIR characteristics, a configuration has been known in which basic multitap direct sampling mixers are arranged in parallel (for example, see Patent Literature 3). FIG. 6 shows a configuration of a discrete time direct sampling mixer disclosed in Patent Literature 3. In addition, FIG. 7 shows clocks supplied to the circuit shown in FIG. 6. FIG. 8A and FIG. 8B show examples of frequency characteristics obtained in the circuit shown in FIG. 6 (local (LO) frequency fLO=800 MHz). By supplying clocks as shown in FIG. 7 to the circuit shown in FIG. 6 having appropriate circuit element values, it is possible to set attenuation poles in the bilateral symmetric positions with respect to the LO frequency as shown in FIG. 8A and FIG. 8B.